The present invention relates to a clock jitter suppressing circuit for suppressing jitter of a clock signal used in a transmission circuit and the like.
In a digital circuit such as a transmission circuit, a clock signal is generally used to set proper timings of various signals. Such a clock signal normally includes phase jitter in which the phase varies over time due to various causes. Control of circuit at accurate timings is interfered with by such jitter. For this reason, a phase-locked loop circuit (to be referred to as a PLL circuit hereinafter) has been used to suppress such phase jitter and obtain a proper clock signal. As such a PLL circuit, an analog PLL circuit has been used, which comprises, e.g., a voltage-controlled oscillator, a low-pass filter, and a feedback circuit.
With the recent remarkable advances in micropatterning of digital ICs, digital circuits having various functions are integrated. However, since such an IC process cannot be directly applied to the above-mentioned analog PLL circuit, a digital PLL circuit formed by digitization based on the principle of an analog PLL has been proposed.
In such a conventional digital PLL circuit, however, processing is simply digitized, and the basic arrangement is still constituted by a feedback circuit and a low-pass filter. With this arrangement, since a transfer function for control is based on an analog quantity in the amplitude direction, the processing and the circuit are inevitably complicated. In addition, if qauntization is forcibly performed to simplify the processing, satisfactory characteristics cannot be obtained.